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? copyright 2006 wiznet co., inc. all ri ghts reserved. 1 W5100 datasheet W5100 datasheet version 1.0.1 ? 2006 wiznet co., inc. all rights reserved. for more information, visit our website at http://www.wiznet.co.kr
? copyright 2006 wiznet co., inc. all ri ghts reserved. 2 W5100 datasheet document history information version date descriptions ver. 1.0.0 dec. 21, 2006 release with W5100 launching ver. 1.0.1 jan. 08, 2007 lb bit in mode regi ster is not used . W5100 is used only in big-endian ordering.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 3 W5100 datasheet wiznet?s online technical support if you have something to ask abou t wiznet products, write down your question on q&a board of ?support? menu in wiznet website ( www.wiznet.co.kr ). wiznet engineer will give an answer as soon as possible. c c l l i i c c k k
? copyright 2006 wiznet co., inc. all ri ghts reserved. 4 W5100 datasheet W5100 datasheet the W5100 is a full-featured, single-chip internet-enabled 10/100 ethernet controller designed for embedded applications where ease of integration, stability, performance, area and system cost control are required. the w5 100 has been designed to facilitate easy implementation of internet connectivity with out os. the W5100 is ieee 802.3 10base-t and 802.3u 100base-tx compliant. the W5100 includes fully hardwire d, market-proven tcp/ip stack and integrated ethernet mac & phy. hardwired tcp/ip stack supports tcp, udp, ipv4, icmp, arp, igmp and pppoe which has been proven in various applications for several years. 16kbytes internal buffer is included for data transmission. no need of consideration for handling ethernet controller, but simple socket programming is required. for easy integration, three different interfaces like memory access way, called direct, indirect bus and spi, are supported on the mcu side. target applications the W5100 is well suited for many embedded applications, including: - home network devices: set-top boxe s, pvrs, digital media adapters - serial-to-ethernet: access controls, led displays, wireless ap relays, etc. - parallel-to-ethernet: pos / mini printers, copiers - usb-to-ethernet: storage devices, network printers - gpio-to-ethernet: home network sensors - security systems: dvrs, network cameras, kiosks - factory and building automation - medical monitoring equipment - embedded servers
? copyright 2006 wiznet co., inc. all ri ghts reserved. 5 W5100 datasheet features - support hardwired tcp/ip protocols : tcp, ud p, icmp, ipv4 arp, igmp, pppoe, ethernet - 10baset/100basetx ethernet phy embedded - support auto negotiation (full-duplex and half duplex) - support auto mdi/mdix - support adsl connection (with support pppoe protocol with pap/chap authentication mode) - supports 4 independent sockets simultaneously - not support ip fragmentation - internal 16kbytes memory for tx/rx buffers - 0.18 m cmos technology - 3.3v operation with 5v i/o signal tolerance - small 80 pin lqfp package - lead-free package - support serial peripheral interface(spi mode 0, 3) - multi-function led outputs (tx, rx, f ull/half duplex, collision, link, speed)
? copyright 2006 wiznet co., inc. all ri ghts reserved. 6 W5100 datasheet block diagram
? copyright 2006 wiznet co., inc. all ri ghts reserved. 7 W5100 datasheet table of contents 1. pin assignment ............................................................... .................................................... 8 1.1 mcu interface signals ............................................................... ................................. 9 1.2 phy signals ............................................................... ............................................... 10 1.3 miscellaneous signals ............................................................... ................................ 11 1.4 power supply signals ............................................................... ................................ 11 1.5 clock signals ............................................................... ............................................ 12 1.6 led signals ............................................................... ............................................... 12 2. memory map ............................................................... ..................................................... 13 3. W5100 registers ............................................................... ................................................ 14 3.1 common registers ............................................................... ..................................... 14 3.2 socket registers ............................................................... ........................................ 15 4. register descriptions ............................................................... ......................................... 18 4.1 common registers ............................................................... .................................... 18 4.2 socket registers ............................................................... ....................................... 25 5. functional descriptions ............................................................... ..................................... 37 5.1 initialization ............................................................... ............................................. 37 5.2.1 tcp ............................................................... ................................................ 40 5.2.1.1 server mode ............................................................... ........................ 41 5.2.1.2 client mode ............................................................... ........................ 47 5.2.2 udp ............................................................... ................................................ 49 5.2.3 ip raw ............................................................... ............................................. 55 5.2.4 mac raw ............................................................... ......................................... 56 6. application information ............................................................... ..................................... 58 6.1 direct bus interface mode ............................................................... ........................ 58 6.2 indirect bus interface mode ............................................................... ..................... 58 6.3 spi (serial peripheral interface) mode ............................................................... ...... 59 6.3.1 device operations ............................................................... .......................... 60 6.3.2 commands ............................................................... ...................................... 60 6.3.3 process of using general spi master device (according to spi protocol) ......... 61 7. electrical specifications ............................................................... .................................... 62 8. ir reflow temperature profile (lead-free) ............................................................... ........ 67 9. package descriptions ............................................................... ......................................... 68
? copyright 2006 wiznet co., inc. all ri ghts reserved. 8 W5100 datasheet 1. pin assignment figure 1. pinout W5100
? copyright 2006 wiznet co., inc. all ri ghts reserved. 9 W5100 datasheet 1.1 mcu interface signals symbol type pin no description /reset i 59 reset this pin is active low input to initialize or re- initialize W5100. by asserting this pin low for at least 2us, all internal registers will be re-initialized to their default states. addr14-0 i 38, 39, 40, 41, 42, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54 address these pins are used to select a register or memory. address pins are internally pulled down. data7-0 i/o 19, 20, 21, 22, 23, 24, 25, 26 data these pins are used to read and write register or memory data. /cs i 55 chip select chip select is for mcu to access to internal registers or memory. /wr and /rd select direction of data transfer. this pin is active low. /int o 56 interrupt this pin indicates that W5100 requires mcu attention after socket co nnecting, disconnecting, data receiving or timeout. the interrupt is cleared by writing ir(interrupt register) or sn_ir (socket nth interrupt register). all interrupts are maskable. this pin is active low. /wr i 57 write enable strobe from mcu to write an internal register/memory selected by addr[14:0]. data is latched into the W5100 on the rising edge of this input. this signal is active low. /rd i 58 read enable
? copyright 2006 wiznet co., inc. all ri ghts reserved. 10 W5100 datasheet strobe from mcu to read an internal register/memory selected by addr[14:0]. this signal is active low. sen i 31 spi enable this pin selects enable/disable of the spi mode. low = spi mode disable high = spi mode enable sclk i 30 spi clock this pin is used to spi clock signal pin. /scs i 29 spi slave select this pin is used to spi slave select signal pin. this pin is active low mosi i 28 spi master out slave in this pin is used to spi mosi signal pin. mios o 27 spi master in slave out this pin is used to spi miso signal pin. 1.2 phy signals symbol type pin no description rxip i 5 rxin i 6 rxip/rxin signal pair the differential data from the media is received on the rxip/rxin signal pair. txop o 8 txon o 9 txop/txon signal pair the differential data is tr ansmitted to the media on the txop/txin signal pair. rset_bg o 1 phy off-chip resistor connect a resistor of 12.3 ? 1% to the ground. refer to the ?reference schematic?. opmode2-0 i 65, 64, 63 operation control mode in auto negotiation operat ion mode, tie them to low
? copyright 2006 wiznet co., inc. all ri ghts reserved. 11 W5100 datasheet 1.3 miscellaneous signals symbol type pin no description test_mode3-0 i 34, 35, 36, 37 W5100 mode select normal mode : 0000 phy test mode : 1111 nc i/o 3,60, 61,62, 78,79, 80 nc test pin for W5100 ( for factory use only) 1.4 power supply signals symbol type pin no description vcc3a3 power 2 3.3v power supply for analog part vcc3d3 power 12, 18, 44 3.3v power supply for digital part vcc18a power 7, 74 1.8v power supply for analog part vcc18d power 15, 16, 33, 69 1.8v power supply for digital part gnda ground 4, 10 77 analog ground gndd ground 13, 14, 17, 32, 43, 68, digital ground v18 o 11 1.8v regulator output voltage
? copyright 2006 wiznet co., inc. all ri ghts reserved. 12 W5100 datasheet 1.5 clock signals symbol type pin no description xtlp i 76 xtln i 75 25mhz crystal input/output a 25mhz parallel-resonant crys tal is used to connect these pins to stabilize the internal oscillator 1.6 led signals symbol type pin no description linkled o 66 link led active low in link state indicates a good status for 10/100m. spdled o 67 link speed led active low indicates the link speed is 100mbps. fdxled o 70 full duplex led active low indicates the status of full-duplex mode. colled o 71 collision led active low indicates the presence of collision activity. rxled o 72 receive activity led active low indicates the presence of receiving activity. txled o 73 transmit activity led active low indicates the presence of transmitting activity.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 13 W5100 datasheet 2. memory map W5100 is composed of common register, socket register, tx memory, and rx memory as shown below. 0x0000 common registers 0x0030 reserved 0x0400 socket registers 0x0800 reserved 0x4000 tx memory 0x6000 rx memory 0x8000 figure 2. memory map
? copyright 2006 wiznet co., inc. all ri ghts reserved. 14 W5100 datasheet 3. W5100 registers 3.1 common registers address register 0x0000 mode (mr) 0x0001 0x0002 0x0003 0x0004 gateway address (gar0) (gar1) (gar2) (gar3) 0x0005 0x0006 0x0007 0x0008 subnet mask address (subr0) (subr1) (subr2) (subr3) 0x0009 0x000a 0x000b 0x000c 0x000d 0x000e source hardware address (shar0) (shar1) (shar2) (shar3) (shar4) (shar5) 0x000f 0x0010 0x0011 0x0012 source ip address (sipr0) (sipr1) (sipr2) (sipr3) 0x0013 0x0014 reserved 0x0015 interrupt (ir) 0x0016 interrupt mask (imr) 0x0017 0x0018 retry time (rtr0) (rtr1) 0x0019 retry count (rcr) address register 0x001a rx memory size (rmsr) 0x001b tx memory size (tmsr) 0x001c 0x001d authentication type in pppoe (patr0) (patr1) 0x001e ~ 0x0027 reserved 0x0028 ppp lcp request timer (ptimer) 0x0029 ppp lcp magic number (pmagic) 0x002a 0x002b 0x002c 0x002d unreachable ip address (uipr0) (uipr1) (uipr2) (uipr3) 0x002e 0x002f unreachable port (uport0) (uport1) 0x0030 ~ 0x03ff reserved
? copyright 2006 wiznet co., inc. all ri ghts reserved. 15 W5100 datasheet 3.2 socket registers address register 0x0400 socket 0 mode (s0_mr) 0x0401 socket 0 command (s0_cr) 0x0402 socket 0 interrupt (s0_ir) 0x0403 socket 0 status (s0_sr) 0x0404 0x0405 socket 0 source port (s0_port0) (s0_port1) 0x0406 0x0407 0x0408 0x0409 0x040a 0x040b socket 0 destinatio n hardware address (s0_dhar0) (s0_dhar1) (s0_dhar2) (s0_dhar3) (s0_dhar4) (s0_dhar5) 0x040c 0x040d 0x040e 0x040f socket 0 destinat ion ip address (s0_dipr0) (s0_dipr1) (s0_dipr2) (s0_dipr3) 0x0410 0x0411 socket 0 destination port (s0_dport0) (s0_dport1) 0x0412 0x0413 socket 0 maximum segment size (s0_mssr0) (s0_mssr1) 0x0414 socket 0 protocol in ip raw mode (s0_proto) address register 0x0415 socket 0 ip tos (s0_tos) 0x0416 socket 0 ip ttl (s0_ttl) 0x0417 ~ 0x041f reserved 0x0420 0x0421 socket 0 tx free size (s0_tx_fsr0) (s0_tx_fsr1) 0x0422 0x0423 socket 0 tx read pointer (s0_tx_rd0) (s0_tx_rd1) 0x0424 0x0425 socket 0 tx write pointer (s0_tx_wr0) (s0_tx_wr1) 0x0426 0x0427 socket 0 rx received size (s0_rx_rsr0) (s0_rx_rsr1) 0x0428 0x0429 socket 0 rx read pointer (s0_rx_rd0) (s0_rx_rd1) 0x042a 0x042b reserved 0x042c ~ 0x04ff reserved address register 0x0500 socket 1 mode (s1_mr) 0x0501 socket 1 command (s1_cr) 0x0502 socket 1 interrupt (s1_ir) 0x0503 socket 1 status (s1_sr) address register 0x0515 socket 1 ip tos (s1_tos) 0x0516 socket 1 ip ttl (s1_ttl)
? copyright 2006 wiznet co., inc. all ri ghts reserved. 16 W5100 datasheet 0x0504 0x0505 socket 1 source port (s1_port0) (s1_port1) 0x0506 0x0507 0x0508 0x0509 0x050a 0x050b socket 1 destinatio n hardware address (s1_dhar0) (s1_dhar1) (s1_dhar2) (s1_dhar3) (s1_dhar4) (s1_dhar5) 0x050c 0x050d 0x050e 0x050f socket 1 destinat ion ip address (s1_dipr0) (s1_dipr1) (s1_dipr2) (s1_dipr3) 0x0510 0x0511 socket 1 destination port (s1_dport0) (s1_dport1) 0x0512 0x0513 socket 1 maximum segment size (s1_mssr0) (s1_mssr1) 0x0514 socket 1 protocol in ip raw mode (s1_proto) 0x0517 ~ 0x051f reserved 0x0520 0x0521 socket 1 tx free size (s1_tx_fsr0) (s1_tx_fsr1) 0x0522 0x0523 socket 1 tx read pointer (s1_tx_rd0) (s1_tx_rd1) 0x0524 0x0525 socket 1 tx write pointer (s1_tx_wr0) (s1_tx_wr1) 0x0526 0x0527 socket 1 rx received size (s1_rx_rsr0) (s1_rx_rsr1) 0x0528 0x0529 socket 1 rx read pointer (s1_rx_rd0) (s1_rx_rd1) 0x052a 0x052b reserved 0x052c ~ 0x05ff reserved address register 0x0600 socket 2 mode (s2_mr) 0x0601 socket 2 command (s2_cr) 0x0602 socket 2 interrupt (s2_ir) 0x0603 socket 2 status (s2_sr) 0x0604 0x0605 socket 2 source port (s2_port0) (s2_port1) address register 0x0615 socket 2 ip tos (s2_tos) 0x0616 socket 2 ip ttl (s2_ttl) 0x0617 ~ 0x061f reserved 0x0620 0x0621 socket 2 tx free size (s2_tx_fsr0) (s2_tx_fsr1) 0x0622 0x0623 socket 2 tx read pointer (s2_tx_rd0) (s2_tx_rd1)
? copyright 2006 wiznet co., inc. all ri ghts reserved. 17 W5100 datasheet 0x0606 0x0607 0x0608 0x0609 0x060a 0x060b socket 2 destinatio n hardware address (s2_dhar0) (s2_dhar1) (s2_dhar2) (s2_dhar3) (s2_dhar4) (s2_dhar5) 0x060c 0x060d 0x060e 0x060f socket 2 destinat ion ip address (s2_dipr0) (s2_dipr1) (s2_dipr2) (s2_dipr3) 0x0610 0x0611 socket 2 destination port (s2_dport0) (s2_dport1) 0x0612 0x0613 socket 2 maximum segment size (s2_mssr0) (s2_mssr1) 0x0614 socket 2 protocol in ip raw mode (s2_proto) 0x0624 0x0625 socket 2 tx write pointer (s2_tx_wr0) (s2_tx_wr1) 0x0626 0x0627 socket 2 rx received size (s2_rx_rsr0) (s2_rx_rsr1) 0x0628 0x0629 socket 2 rx read pointer (s2_rx_rd0) (s2_rx_rd1) 0x062a 0x062b reserved 0x062c ~ 0x06ff reserved address register 0x0700 socket 3 mode (s3_mr) 0x0701 socket 3 command (s3_cr) 0x0702 socket 3 interrupt (s3_ir) 0x0703 socket 3 status (s3_sr) 0x0704 0x0705 socket 3 source port (s3_port0) (s3_port1) 0x0706 0x0707 0x0708 0x0709 0x070a 0x070b socket 3 destinatio n hardware address (s3_dhar0) (s3_dhar1) (s3_dhar2) (s3_dhar3) (s3_dhar4) (s3_dhar5) address register 0x0715 socket 3 ip tos (s3_tos) 0x0716 socket 3 ip ttl (s3_ttl) 0x0717 ~ 0x071f reserved 0x0720 0x0721 socket 3 tx free size (s3_tx_fsr0) (s3_tx_fsr1) 0x0722 0x0723 socket 3 tx read pointer (s3_tx_rd0) (s3_tx_rd1) 0x0724 0x0725 socket 3 tx write pointer (s3_tx_wr0) (s3_tx_wr1)
? copyright 2006 wiznet co., inc. all ri ghts reserved. 18 W5100 datasheet 0x070c 0x070d 0x070e 0x070f socket 3 destinat ion ip address (s3_dipr0) (s3_dipr1) (s3_dipr2) (s3_dipr3) 0x0710 0x0711 socket 3 destination port (s3_dport0) (s3_dport1) 0x0712 0x0713 socket 3 maximum segment size (s3_mssr0) (s3_mssr1) 0x0714 socket 3 protocol in ip raw mode (s3_proto) 0x0726 0x0727 socket 3 rx received size (s3_rx_rsr0) (s3_rx_rsr1) 0x0728 0x0729 socket 3 rx read pointer (s3_rx_rd0) (s3_rx_rd1) 0x072a 0x072b reserved 0x072c ~ 0x07ff reserved 4. register descriptions 4.1 common registers mr (mode register) [r/w] [0x0000] [0x00] this register is used for s/w reset, memory test mode, ping block mode, pppoe mode and indirect bus i/f. 7 6 5 4 3 2 1 0 rst pb pppoe lb ai ind bit symbol description 7 rst s/w reset if this bit is ?1?, internal register will be initialized. it will be automatically cleared after reset. 6 reserved reserved 5 reserved reserved 4 pb ping block mode 0 : disable ping block 1 : enable ping block
? copyright 2006 wiznet co., inc. all ri ghts reserved. 19 W5100 datasheet if the bit is set as ?1?, there is no response to the ping request. 3 pppoe pppoe mode 0 : disable pppoe mode 1 : enable pppoe mode if you use adsl without router or etc, you should set the bit as ?1? to connect to adsl server. for more de tail, refer to the application note, ?how to connect adsl? . 2 not used not used 1 ai address auto-increment in indirect bus i/f 0 : disable auto-increment 1 : enable auto-increment at the indirect bus i/f mode, if this bit is set as ?1?, the address will be automatically increased by 1 whenever read and write are performed. for more detail, refer to ?6.2 indirect bus if mode?. 0 ind indirect bus i/f mode 0 : disable indirect bus i/f mode 1 : enable indirect bus i/f mode if this bit is set as ?1?, indirect bus i/f mode is set. for more detail, refer to ?6. application information?, ?6.2 indirect bus if mode?. gwr (gateway ip address register) [r/w] [0x0001 ? 0x0004] [0x00] this register sets up the default gateway address. ex) in case of ?192.168.0.1? 0x0001 0x0002 0x0003 0x0004 192 (0xc0) 168 (0xa8) 0 (0x00) 1 (0x01) subr (subnet mask register) [r/w] [0x0005 ? 0x0008] [0x00] this register sets up the subnet mask address. ex) in case of ?255.255.255.0? 0x0005 0x0006 0x0007 0x0008 255 (0xff) 255 (0xff) 255 (0xff) 0 (0x00) shar (source hardware address register) [r/w] [0x0009 ? 0x000e] [0x00] this register sets up the source hardware address. ex) in case of ?00.08.dc.01.02.03? 0x0009 0x000a 0x000b 0x000c 0x000d 0x000e
? copyright 2006 wiznet co., inc. all ri ghts reserved. 20 W5100 datasheet 0x00 0x08 0xdc 0x01 0x02 0x03 sipr (source ip address register) [r/w] [0x000f ? 0x0012] [0x00] this register sets up the source ip address. ex) in case of ?192.168.0.3? 0x000f 0x0010 0x0011 0x0012 192 (0xc0) 168 (0xa8) 0 (0x00) 3 (0x03) ir (interrupt register) [r] [0x0015] [0x00] this register is accessed by the host processor to know the cause of an interrupt. any interrupt can be masked in the interrupt mask register (imr). the /int signal retain low as long as any masked signal is set, and will not go high until all masked bits in this register have been cleared. 7 6 5 4 3 2 1 0 conflict unreach pppoe reserved s3_int s2_int s1_int s0_int bit symbol description 7 conflict ip conflict it is set as ?1?, when there is arp requ est with same ip address as source ip address. this bit is cleared to ?0 ? by writing ?1? to this bit. 6 unreach destination unreachable W5100 will receive icmp(des tination unreachable) packet if non-existing destination ip address is transmitted during udp data transmission. (refer to ?5.2.2 udp?). in this case, the ip address and the port number will be saved in unreachable ip address (uipr) and unreachable port register (uport), and the bit will be set as ?1?. this bit will be cleared to ?0? by writing ?1? to this bit. 5 pppoe pppoe connection close in the pppoe mode, if the pppoe connection is closed, ?1? is set. this bit will be cleared to ?0? by writing ?1? to this bit. 4 reserved reserved 3 s3_int occurrence of socket 3 socket interrupt it is set in case that interrupt occu rs at the socket 3. for more detailed information of socket interrupt, refer to ?socket 3 interrupt register (s3_ir)?. this bit will be automatically cleared when s3_ir is cleared to
? copyright 2006 wiznet co., inc. all ri ghts reserved. 21 W5100 datasheet 0x00. 2 s2_int occurrence of socket 2 socket interrupt it is set in case that interrupt occu rs at the socket 2. for more detailed information of socket interrupt , refer to ?socket 2 interrupt register(s2_ir)?. this bit will be automatically cleared when s2_ir is cleared to 0x00. 1 s1_int occurrence of socket 1 socket interrupt it is set in case that interrupt occu rs at the socket 1. for more detailed information of socket interrupt, refe r to ?socket 1 interrupt register (s1_ir)?. this bit will be automatically cleared when s1_ir is cleared to 0x00. 0 s0_int occurrence of socket 0 socket interrupt it is set in case that interrupt occu rs at the socket 0. for more detailed information of socket interrupt, refer to ?socket 0 interrupt register (s0_ir)?. this bit will be automatically cleared when s0_ir is cleared to 0x00. imr (interrupt mask register) [r/w] [0x0016] [0x00] the interrupt mask register is used to mask in terrupts. each interrupt mask bit corresponds to a bit in the interrupt register (ir). if an interru pt mask bit is set, an interrupt will be issued whenever the corresponding bit in the ir is set. if any bit in the imr is set as ?0?, an interrupt will not occur though the bit in the ir is set. 7 6 5 4 3 2 1 0 im_ir7 im_ir6 im_ir5 reserved im_ir3 im_ir2 im_ir1 im_ir0 bit symbol description 7 im_ir7 ip conflict enable 6 im_ir6 destination unreachable enable 5 im_ir5 pppoe close enable 4 reserved it should be set as ?0? 3 im_ir3 occurrence of socket 3 socket interrupt enable 2 im_ir2 occurrence of socket 2 socket interrupt enable 1 im_ir1 occurrence of socket 1 socket interrupt enable 0 im_ir0 occurrence of socket 0 socket interrupt enable
? copyright 2006 wiznet co., inc. all ri ghts reserved. 22 W5100 datasheet rtr (retry time-value register) [r/w] [0x0017 ? 0x0018] [0x07d0] this register sets the period of timeout. value 1 means 100us. the initial value is 2000(0x07d0). that will be set as 200ms. ex) for 400ms configuration, set as 4000(0x0fa0) 0x0017 0x0018 0x0f 0xa0 re-transmission will occu r if there is no response from the remote peer to the commands of connect, discon, close, send, send_mac and send_keep, or the response is delayed. rcr (retry count register) [r/w] [0x0019] [0x08] this register sets the number of re-transmiss ion. if retransmission occurs more than the number recorded in rcr, timeout interrupt (timeout bit of socket n interrupt register (sn_ir) is set as ?1?) will occur. rmsr(rx memory size register) [r/w] [0x001a] [0x55] this register assigns total 8k rx memory to each socket. 7 6 5 4 3 2 1 0 socket 3 socket 2 socket 1 socket 0 s1 s0 s1 s0 s1 s0 s1 s0 the memory size according to the conf iguration of s1, s0 , is as below. s1 s0 memory size 0 0 1kb 0 1 2kb 1 0 4kb 1 1 8kb according to the value of s1 and s0, the memory is assigned to the sockets from socket 0 within the range of 8kb. if there is not enough memory to be assigned, the socket should not be used. the initial value is 0x55 and the 2k memory is assigned to each 4 sockets respectively. ex) when setting as 0xaa, the 4kb memory should be assigned to each socket. however, the total memory size is 8kb. the memory is normally assigned to the socket 0 and 1, but not to the socket 2 and 3. therefore, socket 2 and 3 can not be absolutely used.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 23 W5100 datasheet socket 3 socket 2 socket 1 socket 0 0kb 0kb 4kb 4kb tmsr(tx memory size register) [r/w] [0x001b] [0x55] this register is used in assigning total 8k tx memory to sockets. configuration can be done in the same way of rx memory size register (rmsr). the initial value is 0x55 and it is to assign 2k memory to 4 sockets respectively. patr (authentication type in pppoe mode) [r] [0x001c-0x001d] [0x0000] this register notifies authentication method that has been agreed at the connection with pppoe server. W5100 supports two types of authentication method - pap and chap. value authentication type 0xc023 pap 0xc223 chap ptimer (ppp link control protocol request timer register) [r/w] [0x0028] [0x28] this register indicates the duration for sending lcp echo request. value 1 is about 25ms. ex) in case that ptimer is 200, 200 * 25(ms) = 5000(ms) = 5 seconds pmagic (ppp link control protocol magi c number register) [r/w] [0x0029] [0x00] this register is used in magic number option during lcp negotiation. refer to the application note, ?how to connect adsl? . uipr (unreachable ip address register) [r] [0x002a ? 0x002d] [0x00] in case of data transmission using udp (refer to ?5.2.2. udp?), if trans mitting to non-existing ip address, icmp (destination unreachable) pa cket will be received. in this case, that ip address and port number will be saved in the unreachable ip address register(uipr) and unreachable port register(uport) respectively. ex) in case of ?192.168.0.11?, 0x002a 0x002b 0x002c 0x002d 192 (0xc0) 168 (0xa8) 0 (0x00) 11 (0x0b) uport (unreachable port register) [r] [0x002e ? 0x002f] [0x0000] refer to unreachable ip address register (uipr) ex) in case of 5000(0x1388), 0x002e 0x002f
? copyright 2006 wiznet co., inc. all ri ghts reserved. 24 W5100 datasheet 0x13 0x88
? copyright 2006 wiznet co., inc. all ri ghts reserved. 25 W5100 datasheet 4.2 socket registers s n 1 _mr (socket n mode register) [r/w] [0x0400, 0x0500, 0x0600, 0x0700] [0x00] 2 this register sets up socket option or protocol type for each socket. 7 6 5 4 3 2 1 0 multi nd / mc p3 p2 p1 p0 bit symbol description 7 multi multicasting 0 : disable multicasting 1 : enable multicasting it is applied only in case of udp. for using multicasting, write multicast group address to socket n destination ip and multicast group port number to socket n destination port register, before open command. 6 reserved reserved 5 nd/mc use no delayed ack 0 : disable no delayed ack option 1 : enable no delayed ack option, it is applied only in case of tcp. if this bit is set as ?1?, ack packet is transmitted whenever receiving data pa cket from the peer. if this bit is cleared to ?0?, ack packet is transmitted according to internal timeout mechanism. multicast 0 : using igmp version 2 1 : using igmp version 1 it is applied only in case of multi bit is ?1? 4 reserved reserved 3 p3 2 p2 protocol sets up corresponding socket as tcp, udp, or ip raw mode p3 p2 p1 p0 meaning 0 0 0 0 closed 0 0 0 1 tcp 1 n is socket number (0, 1, 2, 3). 2 [read/write] [address of socket 0, address of socket 1, address of socket 2, address of socket 3] [reset value]
? copyright 2006 wiznet co., inc. all ri ghts reserved. 26 W5100 datasheet 1 p1 0 p0 0 0 1 0 udp 0 0 1 1 ipraw * in case of socket 0, ma craw and pppoe mode exist. p3 p2 p1 p0 meaning 0 1 0 0 macraw 0 1 0 1 pppoe s n _cr (socket n command register) [r/w] [0x0401, 0x0501, 0x0601, 0x0701] [0x00] this register is utilized for socket n initialization, close, connection establishment, termination, data transmission and command receipt. after performing the commands, the register value will be auto matically cleared to 0x00. value symbol description 0x01 open it is used to initialize the socket. according to the value of socket n mode register (s n _mr), socket n status register(s n _sr) value is changed to sock_init, sock_udp, sock_ipraw, or sock_macraw. for more detail, refer to 5. functional description. 0x02 listen it is only used in tcp mode. it changes the value of socket n status register (sn_sr) to sock_listen in order to wait for a connection request from any remote peer (tcp client). for more detail, refer to 5.2.1.1 server mode. 0x04 connect it is only used in tcp mode. it sends a connection request to remote peer(tcp server). if the connection is failed, timeout interrupt will occur. for more detail, refer to 5.2.1.2 client mode. 0x08 discon it is only used in tcp mode. it sends a connection termination requ est. if connection termination is failed, timeout interrupt will occur. for more detail, refer to 5.2.1.1 server mode. * in case of using close command instead of discon, only the value of socket n status register(sn_sr) is changed to sock_closed without the connection termination process. 0x10 close it is used to close the socket. it changes the value of socket n status register(s n _sr) to sock_closed.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 27 W5100 datasheet 0x20 send it transmits the data as much as the increased size of socket n tx write pointer. for more detail, refer to socket n tx free size register (s n _tx_fsr), socket n tx write pointer register(s n _tx_wr), and socket n tx read pointer register(s n _tx_rr) or 5.2.1.1. server mode. 0x21 send_mac it is used in udp mode. the basic operation is same as se nd. normally send operation needs destination hardware address that is received in arp(address resolution protocol) process. send_mac uses socket n destination hardware address(s n _dhar) that is written by users without arp process. 0x22 send_keep it is only used in tcp mode. it checks the connection status by sending 1byte data. if the connection is already terminated or peer has no response, timeout interrupt will occur. 0x40 recv receiving is processed with the value of socket n rx read pointer register(s n _rx_rd). for more detail, refer to 5.2.1.1 server mode receiving process with socket n rx received size register (s n _rx_rsr), socket n rx write pointer register(s n _rx_wr), and socket n rx read pointer register(s n _rx_rd) s n _ir (socket n interrupt register) [r] [0x0402, 0x0502, 0x0602, 0x0702] [0x00] this register is used for notifying connection establishment and termination, receiving data and timeout. the socket n interrupt register must be cleared by writing ?1?. 7 6 5 4 3 2 1 0 reserved reserved reserved send_ok timeout recv discon con bit symbol description 7 reserved reserved 6 reserved reserved 5 reserved reserved 4 send_ok it is set as ?1? if send operation is completed. 3 timeout it is set as ?1? if timeout occurs during connection establishment or termination and data transmission. 2 recv it is set as ?1? if data is received.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 28 W5100 datasheet 1 discon it is set as ?1? if connection termination is requested or finished. 0 con it is set as ?1? if connection is established. s n _sr (socket n status register) [r] [0x0403, 0x0503, 0x0603, 0x0703] [0x00] this register has the status value of socket n . the main status is shown in the below diagram. value symbol description 0x00 sock_closed it is shown in case that close commands are given to s n _cr, and timeout interrupt is asserted or connection is terminated. in this sock_closed status, no operation occurs and all resources for the connection is released. 0x13 sock_init it is shown in case that s n _mr is set as tcp and open
? copyright 2006 wiznet co., inc. all ri ghts reserved. 29 W5100 datasheet commands are given to s n _cr. this is the initial step for tcp connection establishment of a socket. in this sock_init status, the command type (lis ten or connect) of sn_cr will decide the operation type ? tcp server mode or client mode. 0x14 sock_listen it is shown in case that listen commands are given to s n _cr at the sock_init status. the related socket will operate as tcp server mode, an d become estblished status if connection request is normally received. 0x17 sock_established it is shown in case th at connection is established. in this status, tcp data is transmitted and received. 0x1c sock_close_wait it is shown in case that connection termination request is received from peer host . at this status, the acknowledge message has been received from the peer, but not disconnected. the connection can be closed by receiving the dicon or close commands. 0x22 sock_udp it is shown in case that open commands are given to s n _cr when s n _mr is set as udp. as this status does not need the connection process with peer, the data can be directly transmitted and received. 0x32 sock_ipraw it is shown in case that open commands are given to s n _cr when s n _mr is set as ipraw. at the ipraw status, the following protocols of ip header are not processed. refer to ?ip raw? for more information. 0x42 sock_macraw it is shown in case that open commands are given to s0_cr when s0_mr is set as macraw. at the mac raw status, there is no protocol process for a packet. for more information, refer to ?mac raw?. 0x5f sock_pppoe it is shown in case that open commands are given to s0_cr when s0_mr is set as pppoe. below is shown during changing the status. value symbol description 0x15 sock_synsent it is shown in case that connect commands are given to socket n command register(s n _cr) at the sock_init status. it is automatically changed to sock_establish when the connection is established.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 30 W5100 datasheet 0x16 sock_synrecv it is shown in case that connection request is received from remote peer(client). it normally responds to the requests and changes to sock_establish. 0x18 sock_fin_wait 0x1a sock_closing 0x1b sock_time_wait 0x1d sock_last_ack it is shown in the process of connection termination. if the termination is normally processed or timeout interrupt is asserted, it will be automatica lly changed to sock_closed. 0x11 0x21 0x31 sock_arp it is shown when arp request is sent in order to acquire hardware address of remote peer when it sends connection request in tcp mode or sends data in udp mode. if arp reply is received, it changes to the status, sock_synsent, sock_udp or sock_icmp, for the next operation. s n _port (socket n source port register) [r/w] [0 x0404?0x0405, 0x0504?0x0505, 0x0604? 0x0605, 0x0704?0x0705] [0x00] this register sets the source port number for each socket when using tcp or udp mode, and the set-up needs to be made befo re executing the open command. ex) in case of socket 0 port = 5000(0x1388), conf igure as below, 0x0404 0x0405 0x13 0x88 s n _dhar (socket n destination hardware address register) [r/w] [0x0406?0x040b, 0x0506?0x050b, 0x0606?0x060b, 0x0706?0x070b] [0x00] this register sets the destination hardware address of each socket. ex) in case of socket 0 destination hardware address = 08.dc.00.01.02.10, configuration is as below, 0x0406 0x0407 0x0408 0x0409 0x040a 0x040b 0x08 0xdc 0x00 0x01 0x02 0x0a s n _dipr (socket n destination ip address register) [r/w] [0x040c?0x040f, 0x050c?0x050f, 0x060c?0x060f, 0x070c?0x070f] [0x00] this register sets the destination ip address of each socket to be used in setting the tcp connection. in active mode, ip address needs to be set before executing the connect command. in passive mode, W5100 sets up th e connection and then is internally updated
? copyright 2006 wiznet co., inc. all ri ghts reserved. 31 W5100 datasheet with peer ip. ex) in case of socket 0 destination ip address = 192.168.0.11, configure as below. 0x040c 0x040d 0x040e 0x040f 192 (0xc0) 168 (0xa8) 0 (0x00) 11 (0x0b) s n _dport (socket n destination port register) [r/w] [0x0410?0x0411, 0x0510?0x0511, 0x0610?0x0611, 0x0710?0x0711] [0x00] this register sets the destination port number of each socket to be used in setting the tcp connection. in active mode, port number n eeds to be set before executing the connect command. in passive mode, W5100 sets up th e connection and then is internally updated with peer port number. ex) in case of socket 0 destination port = 5000(0x1388), configure as below, 0x0410 0x0411 0x13 0x88 s n _mss (socket n maximum segment size register) [r/w] [0x0412-0x0413, 0x0512- 0x0513, 0x0612-0x0613, 0x0712-0x0713] [0xffff] this register is used for mss (maximum segment si ze) of tcp, and the register displays mss set by the other party when tcp is activated in passive mode. ex) in case of socket 0 mss = 1 460(0x05b4), configure as below, 0x0412 0x0413 0x05 0xb4 s n _proto (socket n ip protocol register) [r/w] [0x0414, 0x0514, 0x0614, 0x0714] [0x00] this ip protocol register is used to set up the protocol field of ip header at the ip layer raw mode. there are several protocol numbers define d in advance by registering to iana. for the overall list of upper level prot ocol identification number that ip is using, refer to online documents of iana (http://www.iana .org/assignments/p rotocol-numbers). ex) internet control message protocol (icmp) = 0x01, internet group management protocol = 0x02 s n _tos (socket n ip type of service register) [r/w] [0x0415,0x0515,0x0615,0x0715]
? copyright 2006 wiznet co., inc. all ri ghts reserved. 32 W5100 datasheet [0x00] this register sets up at the tos field of ip header. s n _ttl (socket n ip time to live register) [r/w] [0x0416,0x0516,0x0616,0x0716] [0x80] this register sets up at the ttl field of ip header. s n _tx_fsr (socket n tx free size register) [r] [0x0420-0x0421, 0x0520-0x0521, 0x0620-0x0621, 0x0720-0x0721] [0x0800] this register notifies the information of da ta size that user can transmit. for data transmission, user should check this value first and control th e size of transmitting data. when checking this register, user should read upper byte(0x0420,0x0520,0x0620,0x0720) first and lower byte(0x0421,0x0521,0x0621,0x0 721) later to get the correct value. ex) in case of 2048(0x0800) in s0_tx_fsr, 0x0420 0x0421 0x08 0x00 total size can be decided according to the value of tx memory size register. in the process of transmission, it will be reduced by the size of transmitting data, and automatically increased after transmission finished. s n _tx_rr (socket n tx read pointer register) [r] [0x0422-0x0423, 0x0522-0x0523, 0x0622-0x0623, 0x0722-0x0723] [0x0000] this register shows the address that transmission is finished at the tx memory. with the send command of socket n command register, it transmits data from current s n _tx_rr to s n _tx_wr and automatically changes after transmission is finished. therefore, after transmission is finished, s n _tx_rr and s n _tx_wr will have same value. when reading this register, user should read upper byte (0x0422, 0x0522, 0x0622, 0x0722) first and lower byte (0x0423, 0x0523, 0x0623, 0x0723) later to get the correct value. s n _tx_wr (socket n tx write pointer register) [r/w] [0x0424-0x0425, 0x0524-0x0525, 0x0624-0x0625, 0x0724-0x0725] [0x0000] this register offers the location information to write the transmission data. when reading this register, user should read upper byte (0x0424, 0x0524, 0x0624, 0x0724) first and lower byte (0x0425, 0x0525, 0x0625, 0x0725) later to get the correct value.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 33 W5100 datasheet ex) in case of 2048(0x0800) in s0_tx_wr, 0x0424 0x0425 0x08 0x00 but this value itself is not the physical addres s to write. so, the physical address should be calculated as follow. 1. socket n tx base address (hereafter we'll call gsn_tx_base) and socket n tx mask address (hereafter we'll call gsn_tx_mask) are calculated on tmsr value. refer to the psedo code of the initialization if the detail is needed. 2. the bitwise-and operation of two values, sn_tx_wr and gsn_tx_mask give result the offset address(hereafter we'll call get_offset ) in tx memory range of the socket. 3. two values get_offset and gsn_tx_base are added together to give result the physical address(hereafter, we'll call get_start_address ). now, write the transmission data to get_start_address as large as you want. (* there's a case that it exceeds the tx memory upper-bound of the socket while writing. in this case, write the transmission data to the upper-bound, and change the physical address to the gsn_tx_base . next, write the rest of the transmission data.) after that, be sure to increase the sn_tx_wr va lue as much as the data size that indicates the size of writing data. finally, gi ve send command to sn_cr(socket n command register). refer to the psedo code of the transmission part on tcp server mode if the detail is needed.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 34 W5100 datasheet calculate physical address
? copyright 2006 wiznet co., inc. all ri ghts reserved. 35 W5100 datasheet s n _rx_rsr (rx received size register) [r] [0x0426-0x0427, 0x0526-0x0527, 0x0626- 0x0627, 0x0726-0x0727] [0x0000] this register notifies the data size received in rx memory. as this value is internally calculated with the values of s n _rx_rd and s n _rx_wr, it is automatically changed by recv command of socket n command register(s n _cr) and receiving data for remote peer. when reading this register, user should read upper byte(0x0426,0x0526,0x0626,0x0726) first and lower byte(0x0427,0x0527,0x0627,0x0727) later to get the correct value. ex) in case of 2048(0x0800) in s0_rx_rsr, 0x0426 0x0427 0x08 0x00 the total size of this value can be decided according to the value of rx memory size register. s n _rx_rd (socket n rx read pointer register) [r/w] [0x0428-0x0429, 0x0528-0x0529, 0x0628-0x0629, 0x0728-0x0729] [0x0000] this register offers the location information to read the receiving data. when reading this register, user should read upper byte (0x0428, 0x0528, 0x0628, 0x0728) first and lower byte (0x0429, 0x0529, 0x0629, 0x0729) later to get the correct value. ex) in case of 2048(0x0800) in s0_rx_rd, 0x0428 0x0429 0x08 0x00 but this value itself is not the physical addre ss to read. so, the physical address should be calculated as follow. 1. socket n rx base address (hereafter we'll call gsn_rx_base) and socket n rx mask address (hereafter we'll call gsn_rx_mask) are calculated on rmsr value. refer to the pseudo code of the 5.1 initialization if the detail is needed. 2. the bitwise-and operation of two values, sn_rx_rd and gsn_rx_mask give result the offset address(hereafter we'll call get_offset) , in rx memory range of the socket. 3. two values get_offset and gsn_rx_base are added together to give result the physical address(hereafter, we'll call get_start_address). now, read the receiving data from get_start_address as large as you want. (* there's a case that it exceeds the rx memory upper-bound of the socket while reading. in this case, read the receiving data to the upper-bound, an d change the physical address to the gsn_rx_base . next, read the rest of the receiving data.) after that, be sure to increase the sn_rx_rd value as large as the data size that indicates the size of reading data. (* must not increase more than the size of received data. so must check sn_rx_rsr before receiving process.) fina lly, give recv command to sn_cr(socket n
? copyright 2006 wiznet co., inc. all ri ghts reserved. 36 W5100 datasheet command register). refer to the pseudo code of the receiving part on tcp server mode if the detail is needed.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 37 W5100 datasheet 5. functional descriptions by setting some register and memory operation , W5100 provides internet connectivity. this chapter describes how it can be operated. 5.1 initialization ? basic setting for the W5100 operation, select and utilize appropriate registers shown below. 1. mode register (mr) 2. interrupt mask register (imr) 3. retry time-value register (rtr) 4. retry count register (rcr) for more information of above registers, refer to the ?register descriptions?. ? setting network information below register is for basic network configuration information to be configured according to the network environment. 1. gateway address register (gar) 2. source hardware address register (shar) 3. subnet mask register (subr) 4. source ip address register (sipr) the source hardware address register (shar) is the h/w address to be used in mac layer, and can be used with the address that manufacture r has been assigned. the mac address can be assigned from ieee. for more detail, refer to ieee homepage. ? set socket memory information this stage sets the socket tx/rx memory information. the base address and mask address of each socket are fixed and saved in this stage. in case of, assign 2k rx memory per socket. { rmsr = 0x55; // assign 2k rx memory per socket. gs0_rx_base = chip_base_address + rx_memory_base_address(0x6000); gs0_rx_mask = 2k ? 1 ; // 0x07ff, for getting offset address within assigned socket 0 rx memory. gs1_rx_base = gs0_base + (gs0_mask + 1); gs1_rx_mask = 2k ? 1 ;
? copyright 2006 wiznet co., inc. all ri ghts reserved. 38 W5100 datasheet gs2_rx_base = gs1_base + (gs1_mask + 1); gs2_rx_mask = 2k ? 1 ; gs3_rx_base = gs2_base + (gs2_mask + 1); gs3_rx_mask = 2k ? 1 ; tmsr = 0x55; // assign 2k tx memory per socket. same method, set gs0_tx_base, gs0_t x_mask, gs1_tx_base, gs1_tx_mask, gs2_tx_base, gs2_tx_mask, gs3_tx_base and gs3_tx_mask. } in case of, assign 4k,2k,1k,1k. { rmsr = 0x06; // assign 4k,2k,1k,1k rx memory per socket. gs0_rx_base = chip_base_address + rx_memory_base_address(0x6000); gs0_rx_mask = 4k ? 1 ; // 0x0fff, for getting offset address within assigned socket 0 rx memory. gs1_rx_base = gs0_base + (gs0_mask + 1); gs1_rx_mask = 2k ? 1 ; // 0x07ff gs2_rx_base = gs1_base + (gs1_mask + 1); gs2_rx_mask = 1k ? 1 ; // 0x03ff gs3_rx_base = gs2_base + (gs2_mask + 1); gs3_rx_mask = 1k ? 1 ; // 0x03ff tmsr = 0x06; // assign 4k,2k,1k,1k rx memory per socket. same method, set gs0_tx_base, gs0_t x_mask, gs1_tx_base, gs1_tx_mask, gs2_tx_base, gs2_tx_mask, gs3_tx_base and gs3_tx_mask. }
? copyright 2006 wiznet co., inc. all ri ghts reserved. 39 W5100 datasheet
? copyright 2006 wiznet co., inc. all ri ghts reserved. 40 W5100 datasheet 5.2 data communications data communication is available through tcp, udp, ip-raw and mac-raw . in order to select it, configure protocol field of socket n mode register(s n _mr) of the communication sockets (W5100 supports total 4 sockets). 5.2.1 tcp tcp is the connection based communication method that will establish connection in advance and deliver the data through the connection by using ip address and port number of the systems. there are two methods to establish the connection. one is server mode(passive open) that is waiting for connection request. the other is client mode (active open) that sends connection request to a server.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 41 W5100 datasheet 5.2.1.1 server mode ? socket initialization in order to initialize a socket, set the oper ation mode and port of the socket, and provide open command to the command register of th e socket. below is the registers related. socket n mode register (sn_mr) socket n source port register (sn_port) socket n command register (sn_cr) it initializes the socket n as tcp, { start: /* sets tcp mode */ sn_mr = 0x01; /* sets source port number */ sn_port = source_port;
? copyright 2006 wiznet co., inc. all ri ghts reserved. 42 W5100 datasheet /* sets open command */ sn_cr = open; if (sn_sr != sock_init) sn _cr = close; goto start; } ? listen set the listen command to the command re gister. the related register is below. socket n command register (sn_cr) { /* listen socket */ sn_cr = listen; if (sn_sr != sock_listen) sn _cr = close; goto start; // check socket status } ? established ? if connection request is received from remot e peer (the status of sock_synrecv), W5100 sends ack packet and changes to sock_established status. this status can be checked as below. first method : { if (sn_ir(con bit) == ?1?) go to established stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ } second method : { if (sn_sr == sock_established) goto established stage; } as connection is establishe d, data transmission and receipt can be performed. ? established : received data ?
? copyright 2006 wiznet co., inc. all ri ghts reserved. 43 W5100 datasheet check as below to know if data is received from remote peer or not. first method : { if (sn_ir(recv bit) == ?1?) goto receiving process stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ } second method : { if (sn_rx_rsr != 0x0000) goto receiving process stage; } ? established : receiving process received data can be processed as below. { /* first, get the received size */ get_size = sn_rx_rsr; /* calculate offset address */ get_offset = sn_rx_rd & gsn_rx_mask; /* calculate start address(physical address) */ get_start_address = gsn_rx_base + get_offset; /* if overflow socket rx memory */ if ( (get_offset + get_size) > (gsn_rx_mask + 1) ) { /* copy upper_size bytes of get_start_address to destination_addr */ upper_size = (gsn_rx_mask + 1) ? get_offset; memcpy(get_start_address, destination_addr, upper_size); /* update destination_addr */ destination_addr += upper_size; /* copy left_size bytes of gsn_rx_base to destination_addr */ left_size = get_size ? upper_size; memcpy(gsn_rx_base, destination_addr, left_size); } else
? copyright 2006 wiznet co., inc. all ri ghts reserved. 44 W5100 datasheet { /* copy get_size bytes of get_start_address to destination_addr */ memcpy(get_start_address, destination_addr, get_size); } /* increase sn_rx_rd as length of get_size */ sn_rx_rd += get_size; /* set recv command */ sn_cr = recv; } ? established : send data ? / sending process the sending procedure is as below. { /* first, get the free tx memory size */ freesize: get_free_size = sn_tx_fsr; if (get_free_size < send _size) goto freesize; /* calculate offset address */ get_offset = sn_tx_wr & gsn_tx_mask; /* calculate start address(physical address) */ get_start_address = gsn_tx_base + get_offset; /* if overflow socket tx memory */ if ( (get_offset + send_siz e) > (gsn_tx_mask + 1) ) { /* copy upper_size bytes of source_addr to get_start_address */ upper_size = (gsn_tx_mask + 1) ? get_offset; memcpy(source_addr, get_start_address, upper_size); /* update source_addr */ source_addr += upper_size; /* copy left_size bytes of source_addr to gsn_tx_base */ left_size = send_size ? upper_size; memcpy(source_addr, gsn_ tx_base, left_size); } else
? copyright 2006 wiznet co., inc. all ri ghts reserved. 45 W5100 datasheet { /* copy send_size bytes of source_addr to get_start_address */ memcpy(source_addr, get_start_address, send_size); } /* increase sn_tx_wr as length of send_size */ sn_tx_wr += send_size; /* set send command */ sn_cr = send; } ? established : received fin? waiting for a connection termination request from remote peer. it can be checked as below if it received connection termination request of remote peer. first method : { if (sn_ir(discon bit) == ?1?) goto closed stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ } second method : { if (sn_sr == sock_close_wai t) goto closed stage; } ? established : disconnect ? / disconnecting process check if user requests to terminate this connection. to terminate the connection, proceed as below, { /* set discon command */ sn_cr = discon; } ? established : closed ? no connection state at all. it can be checked as below,
? copyright 2006 wiznet co., inc. all ri ghts reserved. 46 W5100 datasheet first method : { if (sn_ir(discon bit) == ?1?) goto closed stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ } second method : { if (sn_sr == sock_closed) goto closed stage; } ? established : timeout in case that connection is closed due to the er ror of remote peer during data receiving or connection closing process, data transmission ca n not be normally processed. at this time timeout occurs after some time. first method : { if (sn_ir(timeout bit) == ?1?) goto closed stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ } second method : { if (sn_sr == sock_closed) goto closed stage; } ? socket close this process should be processed in case that connection is closed after data exchange, socket should be closed with timeout occurr ence, or forcible disconnection is necessary due to abnormal operation. { /* set close command */ sn_cr = close; }
? copyright 2006 wiznet co., inc. all ri ghts reserved. 47 W5100 datasheet 5.2.1.2 client mode whole process is shown as below. ? socket initialization refer to ?5.2.1.1 server mode? (t he operation is same as server). ? connect send connection request to remo te host(server) is as below. { /* write the value of server_ip, server_port to the socket n destination ip address register(s n _dipr), socket n destination port register(s n _dport). */ sn_dipr = server_ip; sn_dport = server_port; /* set connect command */
? copyright 2006 wiznet co., inc. all ri ghts reserved. 48 W5100 datasheet sn_cr = connect; } ? established ? the connection is established. it can be checked as below, first method : { if (sn_ir(con bit) == ?1?) go to established stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ } second method : { if (sn_sr == sock_established) goto established stage; } ? timeout socket is closed as timeout occurs as there is not response from remote peer. it can be checked as below. first method : { if (sn_ir(timeout bit) == ?1?) goto closed stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ } second method : { if (sn_sr == sock_closed) goto closed stage; } ? established refer to ?5.2.1.1. server mode? (the operation is same as server mode)
? copyright 2006 wiznet co., inc. all ri ghts reserved. 49 W5100 datasheet 5.2.2 udp udp provides unreliable and connectionless data gram transmission structure. it processes data without connection establishment. theref ore, udp message can be lost, overlapped or reversed. as packets can arrive faster, recipient can not process all of them. in this case, user application should guarantee the reliability of data transmission. udp transmission can be processed as below, ? socket initialization initialize the socket n as udp. { start: /* sets udp mode */ sn_mr = 0x02; /* sets source port number */ /* the value of source port can be appropriat ely delivered when remote host knows it. */ sn_port = source_port; /* sets open command */ sn_cr = open; /* check if the value of socket n status register(s n _sr) is sock_udp. */ if (sn_sr != sock_udp) sn_cr = close; goto start; } ? received data?
? copyright 2006 wiznet co., inc. all ri ghts reserved. 50 W5100 datasheet it can be checked as below if data is received from remote peer. first method : { if (sn_rx_rsr != 0x0000) goto receiving process stage; } second method : { if (sn_ir(recv bit) == ?1?) goto receiving process stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ } ? receiving process received data can be processed as below. in case of udp, 8byte header is attached to receiving data. the structure of the header is as below. { /* first, get the received size */ get_size = sn_rx_rsr; /* calculate offset address */ get_offset = sn_rx_rd & gsn_rx_mask; /* calculate start address(physical address) */ get_start_address = gsn_rx_base + get_offset; /* read head information (8 bytes) */ header_size = 8;
? copyright 2006 wiznet co., inc. all ri ghts reserved. 51 W5100 datasheet /* if overflow socket rx memory */ if ( (get_offset + header_siz e) > (gsn_rx_mask + 1) ) { /* copy upper_size bytes of get_start_address to header_addr */ upper_size = (gsn_rx_mask + 1) ? get_offset; memcpy(get_start_address, header_addr, upper_size); /* update header_addr */ header_addr += upper_size; /* copy left_size bytes of gsn_rx_base to header_addr */ left_size = header_size ? upper_size; memcpy(gsn_rx_base, header_addr, left_size); /* update get_offset */ get_offset = left_size; } else { /* copy header_size bytes of get_start_address to header_addr */ memcpy(get_start_address, header_addr, header_size); /* update get_offset */ get_offset += header_size; } /* update get_start_address */ get_start_address = gsn_rx_base + get_offset; /* save remote peer informatio n & received data size */ peer_ip = header[0 to 3]; peer_port = header[4 to 5]; get_size = header[6 to 7]; /* if overflow socket rx memory */ if ( (get_offset + get_size) > (gsn_rx_mask + 1) ) { /* copy upper_size bytes of get_start_address to destination_addr */ upper_size = (gsn_rx_mask + 1) ? get_offset; memcpy(get_start_address, destination_addr, upper_size); /* update destination_addr */ destination_addr += upper_size;
? copyright 2006 wiznet co., inc. all ri ghts reserved. 52 W5100 datasheet /* copy left_size bytes of gsn_rx_base to destination_addr */ left_size = get_size ? upper_size; memcpy(gsn_rx_base, destination_addr, left_size); } else { /* copy get_size bytes of get_start_address to destination_addr */ memcpy(get_start_address, destination_addr, get_size); } /* increase sn_rx_rd as length of get_size+header_size */ sn_rx_rd = sn_rx_rd + get_size + header_size; /* set recv command */ sn_cr = recv; } ? send data? / sending process data transmission process is as below. { /* first, get the free tx memory size */ freesize: get_free_size = sn_tx_fsr; if (get_free_size < send _size) goto freesize; /* write the value of remote_ip, remote_port to the socket n destination ip address register(s n _dipr), socket n destination port register(s n _dport). */ sn_dipr = remote_ip; sn_dport = remote_port; /* calculate offset address */ get_offset = sn_tx_wr & gsn_tx_mask; /* calculate start address(physical address) */ get_start_address = gsn_tx_base + get_offset; /* if overflow socket tx memory */ if ( (get_offset + send_siz e) > (gsn_tx_mask + 1) ) {
? copyright 2006 wiznet co., inc. all ri ghts reserved. 53 W5100 datasheet /* copy upper_size bytes of source_addr to get_start_address */ upper_size = (gsn_tx_mask + 1) ? get_offset; memcpy(source_addr, get_start_address, upper_size); /* update source_addr */ source_addr += upper_size; /* copy left_size bytes of source_addr to gsn_tx_base */ left_size = send_size ? upper_size; memcpy(source_addr, gsn_ tx_base, left_size); } else { /* copy send_size bytes of source_addr to get_start_address */ memcpy(source_addr, get_start_address, send_size); } /* increase sn_tx_wr as length of send_size */ sn_tx_wr += send_size; /* set send command */ sn_cr = send; } ? complete sending? the sending completion should be checked after send command. { if (sn_cr == 0x00) transmission is completed. } ? timeout timeout occurs if remote peer does not exist or data transmission is not normally processed. it can be checked as below. { if (sn_ir(timeout bit) == ?1?) goto next stage; /* in this case, if the interrupt of socket n is activated, interrupt occurs. refer to interrupt register(ir), interrupt mask register (imr) and socket n interrupt register (sn_ir). */ }
? copyright 2006 wiznet co., inc. all ri ghts reserved. 54 W5100 datasheet ? finished? / socket close if all the actions are finished, close the socket. { /* set close command */ sn_cr = close; }
? copyright 2006 wiznet co., inc. all ri ghts reserved. 55 W5100 datasheet 5.2.3 ip raw ip raw mode can be utilized if transport layer pr otocol of some icmp or igmp that W5100 does not support, needs to be processed. ? socket initialization it initializes the socket as ip raw. { start: /* sets ip raw mode */ sn_mr = 0x03; /* sets protocol value */ /* the value of protocol is used in protocol field of ip header. for the list of protocol identification number of upper classification, refer to on line documents of iana (http://www.iana .org/assignments /protocol-numbers ). */ sn_proto = protocol_value; /* sets open command */ sn_cr = open; /* check if the value of socket n status register(s n _sr) is sock_ipraw. */ if (sn_sr != sock_ipraw) sn_cr = close; goto start; }
? copyright 2006 wiznet co., inc. all ri ghts reserved. 56 W5100 datasheet ? received data? it is same as udp. refer to ?5.2.2 udp?. ? receiving process this is same as udp. refer to ?5.2.2 udp? except the header information and header size. in case of ip raw, 6byte header is attached to the data received. the header structure is as below. ? send data? / sending process this is same as udp. refer to ?5.2.2 udp? except that remote_port information is not needed. ? complete sending ? timeout ? finished? / socket closed next actions are same as udp. refer to ?5.2.2 udp?. 5.2.4 mac raw mac raw mode(only supported in socket 0) can be utilized. ? socket initialization it initializes the socket as mac raw. { start: /* sets mac raw mode */
? copyright 2006 wiznet co., inc. all ri ghts reserved. 57 W5100 datasheet sn_mr = 0x04; /* sets open command */ sn_cr = open; /* check if the value of socket n status register(s n _sr) is sock_macraw. */ if (sn_sr != sock_macraw) sn_cr = close; goto start; } ? received data? this is same as udp. refer to ?5.2.2 udp?. ? receiving process mac raw received ethernet packet having packet size information. in case of mac raw, 2byte header is attached to the data received. the header structure is as below. ? send data? / sending process this is same as udp. refer to ?5.2.2 udp? except that remote_port information is not needed.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 58 W5100 datasheet 6. application information for the communication with mcu, W5100 provides direct, indirect bus i/f, and spi i/f modes. for the communication with et hernet phy, mii is used. 6.1 direct bus interface mode direct bus i/f mode uses 15bit address line and 8bit data line, /cs, /rd, /wr, /int. 6.2 indirect bus interface mode indirect bus i/f mode uses 2bit address line and 8bit data line, /cs, /rd, /wr, /int. [14:2], other addre ss lines should process pull-down. indirect bus i/f mode related register is as below.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 59 W5100 datasheet value symbol description 0x00 mr it performs the selection of indirect bus i/f mode, address automatic increase. refer to ?4. register description? for more detail. 0x01 0x02 idm_ar0 idm_ar1 indirect bus i/f mode address register big-endian use only in case of big-endian ordering 0x01 0x02 idm_ar0 : msb idm_ar1 : lsb ex) in case of reading s0_cr(0x0401), 0x01(idm_ar0) 0x02(idm_ar1) 0x04 0x01 0x03 idm_dr indirect bus i/f mode data register in order to read or write the internal register or internal tx/rx memory, 1. write the address to read or write on idm_ar0, 1. 2. read or write idm_dr. in order to read or write the data on the sequ ential address, set ai bit of mr(mode register). with this, user performs above 1 only one time . whenever read or write idm_dr, idm_ar , the value is automatically increased by 1. ther efore, the value can be processed on the sequential address just by continuous reading or writing of idm_dr. 6.3 spi (serial peripheral interface) mode serial peripheral interface mode uses only four pins for data communication. four pins are sclk , /ss, mosi, miso. at the W5100, spi_en pin is used for spi operation. by asserting spi_en pin high, a[14~11] pi ns turn to sclk, /ss, mosi, miso pins.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 60 W5100 datasheet 6.3.1 device operations the W5100 is controlled by a set of instruction th at is sent from a host controller, commonly referred to as the spi master. the spi master communicates with W5100 via the spi bus which is composed of four signal li nes: slave select(/ss), serial cl ock(sclk), mosi(master out slave in), miso(master in slave out). the spi protocol defines four modes for its op eration (mode 0, 1, 2, 3). each mode differs according to the sclk polarity and phase - ho w the polarity and phase control the flow of data on the spi bus. the W5100 operates as spi slave device and su pports the most common modes - spi mode 0 and 3. the only difference between spi mode 0 and 3 is the polarity of the sclk signal at the inactive state. with spi mode 0 and 3, data is always latched in on the rising edge of sclk and always output on the falling edge of sclk. 6.3.2 commands according to spi protocol, there are only two data lines used between spi devices. so, it is necessary to define op-code. W5100 uses two types of op-code - read op-code and write op-code. except for those two op-codes, w510 0 will be ignored and no operation will be started. in spi mode, W5100 operates in ?unit of 32-bit stream?. the unit of 32-bit stream is composed of 1 by te op-code field, 2 bytes address field and 1 byte data field. op-code, address and data bytes are transferred with the most significant bit(msb) first and least significant bit(lsb) last. in other words, th e first bit of spi data is msb of op-code field
? copyright 2006 wiznet co., inc. all ri ghts reserved. 61 W5100 datasheet and the last bit of spi data is lsb of data -field. W5100 spi data format is as below. command op-code field address field data field write operation 0xf0 1111 0000 2 bytes 1 byte read operation 0x0f 0000 1111 2 bytes 1 byte 6.3.3 process of using gene ral spi master device (according to spi protocol) 1. configure input/output direction on spi master device pins. * /ss (slave select) : output pin * sclk (serial clock) : output pin * mosi (master out slave in) : output pin * miso (master in slave out) : input pin 2. configure /ss as ?high? 3. configure the registers on spi master device. * spi enable bit on spcr register (spi control register) * master/slave select bit on spcr register * spi mode bit on spcr register * spi data rate bit on spcr re gister and spsr register (spi state register) 4. write desired value for transmission on spdr register (spi data register). 5. configure /ss as ?low? (data transfer start) 6. wait for reception complete 7. if all data transmission en ds, configure /ss as ?high?
? copyright 2006 wiznet co., inc. all ri ghts reserved. 62 W5100 datasheet 7. electrical specifications absolute maximum ratings symbol parameter rating unit v dd dc supply voltage -0.5 to 3.6 v v in dc input voltage -0.5 to 5.5 (5v tolerant) v i in dc input current 5 ma t op operating temperature 0 to 80 c t stg storage temperature -55 to 125 c *comment : stressing the device beyond the ?absol ute maximum ratings? may cause permanent damage. dc characteristics symbol parameter test condition min typ max unit v dd dc supply voltage junction temperature is from -55 c to 125 c 3.0 3.6 v v ih high level input voltage 2.0 5.5 v v il low level input voltage - 0.5 0.8 v v oh high level output voltage i oh = 2, 4, 8, 12, 16, 24 ma 2.0 3.6 v v ol low level output voltage i ol = -2, -4, -8, -12, - 16, -24 ma 0.0 0.4 v i i input current v in = v dd 5 a power dissipation symbol parameter test condition min typ max unit p 10base power consumption in 10baset ma p 100base power consumption in 100baset ma
? copyright 2006 wiznet co., inc. all ri ghts reserved. 63 W5100 datasheet ac characteristics reset timing symbol parameter min max t rst reset cycle time 2 us - t rlc /reset to internal plock - 10 ms register/memory read timing symbol parameter min max t rc read cycle time 80 ns - t cvo /cs to valid output - 80 ns
? copyright 2006 wiznet co., inc. all ri ghts reserved. 64 W5100 datasheet t rvo /rd to valid output - 80 ns t clz /cs to low-z output 0 ns - t rlz /rd to low-z output 0 ns - t chz /cs to high-z output - 1 ns t rhz /rd to high-z output - 1 ns register/memory write timing symbol parameter min max t wc write cycle time 70 ns - t cw /cs to write end 70 ns - t wp /wr pulse width 63 ns - t sd /wr low to sd valid - 14 ns t hd data hold from write end 0 ns -
? copyright 2006 wiznet co., inc. all ri ghts reserved. 65 W5100 datasheet spi timing description mode min max 1 /ss low to sclk slave 21 ns - 2 input setup time slave 7 ns - 3 input hold time slave 28 ns - 4 output setup time slave 7 ns 14 ns 5 output hold time slave 21 ns - 6 slkc time slave 70 ns
? copyright 2006 wiznet co., inc. all ri ghts reserved. 66 W5100 datasheet crystal characteristics parameter range frequency 25 mhz frequency tolerance (at 25 ) 30 ppm shunt capacitance 7pf max drive level 1 ~ 500uw (100uw typical) load capacitance 18pf, 20pf, 27pf, 30pf, 32pf, or specify operating temperature range -10 ~ 60 aging (at 25 ) 3ppm / year max transformer characteristics parameter tra n sm i t en d receive end turn ratio 1:1 1:1 inductance 350 uh 350 uh symmetrical tx & rx channels for auto mdi/mdix capability
? copyright 2006 wiznet co., inc. all ri ghts reserved. 67 W5100 datasheet 8. ir reflow temperature profile (lead-free) moisture sensitivity level : 3 dry pack required : yes average ramp-up rate (ts max to tp) 3 c/second max. preheat C te m p e r a t u r e m i n ( ts min ) C te m p e r a t u r e m a x ( ts max ) C time (ts min to ts max ) 150 c 200 c 60-180 seconds time maintained above: C te m p e r a t u r e ( t l ) C time (tl) 217 c 60-150 seconds peak/classification temperature (tp) 260 + 0 c time within 5 c of actual peak temperature (tp) 20-40 seconds ramp-down rate 6 c/second max. time 25 c to peak temperature 8 minutes max.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 68 W5100 datasheet 9. package descriptions millimeter inch symbol min. nom. max. min. nom. max. a - - 1.60 - - 0.063 a1 0.05 - 0.15 0.002 - 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 12.00 bsc. 0.472 bsc.
? copyright 2006 wiznet co., inc. all ri ghts reserved. 69 W5100 datasheet d1 10.00 bsc. 0.393 bsc. e 12.00 bsc. 0.472 bsc. e1 10.00 bsc. 0.393 bsc. r2 0.08 - 0.20 0.003 - 0.008 r1 0.08 - - 0.003 - - 0 3.5 7 0 3.5 7 1 0 - - 0 - - 2 11 12 13 11 12 13 3 11 12 13 11 12 13 c 0.09 - 0.20 0.004 - 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 - - 0.008 - - b 0.13 0.16 0.23 0.005 0.006 0.009 e 0.40 bsc 0.016 bsc d2 7.60 0.299 e2 7.60 0.299 aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.07 0.003 note : 1. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0. 25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 2. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.

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